|General Purpose Fixed-point DSP MAC Times (ns)|
1/ The reduction in cycle times around the turn of the century as we moved to modern VLIW/SIMD architectures.
2/ The squeeze on cycle times that has happened since the mid 2000s, in fact, if we were to put in 2014s figure it would be little different to the 0.8 of 2011.
Going forward it will be interesting to see if what technology, if anything, will come along that will allow future clock speed upgrades so that the DSP manufacturers don't just have to rely on parallel processing to provide increased performance.
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